FastReduce Module
Functions and values
Function or value | Description |
Full Usage:
assertThat cond msg
Parameters:
bool
msg : string
Modifiers: inline |
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Full Usage:
extractBit fd busWidth
Parameters:
FastData
busWidth : int
Returns: uint32
Modifiers: inline |
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Full Usage:
extractBitFData fd_ busWidth
Parameters:
FData
busWidth : int
Returns: uint32
Modifiers: inline |
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Full Usage:
fastReduce maxArraySize numStep isClockedReduction comp
Parameters:
int
numStep : int
isClockedReduction : bool
comp : FastComponent
Returns: Unit
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Given a component, compute its outputs from its inputs, which must already be evaluated. Outputs and inputs are both contained as time sequences in arrays. This function will calculate simStep outputs from (previously calculated) simStep outputs and clocked (simStep-1) outputs. Memory has state separate from simStep-1 output, for this the state is recalculated. Inputs and outputs come from either UInt32Step or BigIntStep arrays in IOArray record.
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Full Usage:
fastReduceFData maxArraySize numStep isClockedReduction comp
Parameters:
int
numStep : int
isClockedReduction : bool
comp : FastComponent
Returns: Unit
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Version of fastReduce which operates on the IOArray.FDataStep arrays, and simulates using posibly algebraic data. Given the input port values for a component comp, work out its output in the same clock cycle. Used by TruthTable simulations, which use FData type that includes algebraic data. Because TruthTable simulations are only combinational the match statement is much simpler than normal FastReduce. Clocked operations need not be implemented.
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