Raised when an Algebraic case is found in FastSim which has not been implemented, or does not make sense to implement.

Used for efficiency reasons. For a given normal simulation these arrays show whether the corresponding component input or output is a bigint or a unint32 type bus, and therefore show IOArray array is used for the data.

Binary data used in simulation

Convenience array used so that waveform simulation can access component outputs (drivers) without a Map lookup

FastComponent represents a physical component in a simulation. Because sheets can be instantiated in multiple places a given sheet component can have multiple FastComponents in the simulation. Arrays on FastComponent are filled up with simulation data per clock step as a clocked simulation progresses.

GatherTemp is the output type used to accumulate lists of data links when recursively exploring SimulationGraph as first step in flattening it. Each list of pairs is converted into a map at the end in the final GatherData structure The cost of creating maps makes it important to use lists here as the intermediate structures

This type represents an array of time steps of simulation data. In any simulation, for a given IOArray, only one of the three 'Step' arrays will be used. For (very strong) efficiency reasons this cannot be implemented as a disjoint union: the code that reads and writes IOArray array elements will access the appropriate array. Truthtable simulations use FDataStep everywhere. Normal simulations use UInt32step or BigIntStep according to the size of the relevant bus.

Message used to feed forward evaluation. Clock tick => state changes to that in next cycle

State retrieves directly from Diagram has Javascript objects

Wrapper for Javascript (Diagram) component. Why here?

Wrapper for Javascript (Diagram) connection. Why here?

contains info needed to propagate wire value changes through a simulation.

This drives the generation of component outputs it is processed by the Reducer function.

When all inputs are available the reducer function will generate these outputs. For custom components the SimulationGraph contains embedded state.

Type used to tie component ports to simulation data for advanved wavefor simulation features.

Like Component but with additional dynamic info used by simulator Clocked components have state data. All components have optional data on inputs that propagates During evaluation of combinational logic Components require all inputs to have data before they can generate output data Note that reducer is a function that generates the outputs TODO: make this equatable data?

State (possibly none) remembered by component from previous clock cycle. Combinational components have no state.

- Top level data tracking a simulation

- Documents an error found while simulating. - Should never happen

Map every ComponentId to its SimulationComponent.

For every IO node, keep track of its Id, Label and wire width. - Id: to feed values into the simulationGraph. - Label: to display a nice form to the user. - Width: to feed the right values into the simulation.

document current status of a simulation as used by waveform simulator

Wrapper to allow arrays to be resized for longer simulations while keeping the links between inputs and outputs

Fixed width bus data used in simulation TODO: refactor as int64 or bigint for efficiency The list is little-endian: the LSB is at index 0, and the MSB is at index N-1, where N is the length of the list.